VLSI Engineering

A Blog for VLSI Evangelists.

Wednesday, December 30, 2015

Verification


Posted by Sreyas Nampoothiri at 10:54 PM No comments:
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Labels: PERL, Python, Scripting, TCL, TK Toolkit, Verification

Static Timing Analysis


Posted by Sreyas Nampoothiri at 10:54 PM No comments:
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Labels: ASIC, Timing Analysis
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Contributors

  • JOHN_07
  • Sreyas Nampoothiri
  • Surabhi B R

Blog Archive

  • ▼  2015 (2)
    • ▼  December (2)
      • Verification
      • Static Timing Analysis
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